Catalyst Semiconductor CAT28C17A free download

File name 28C17A.pdf

CAT28C17A 16K-Bit CMOS PARALLEL E2PROM FEATURES s Fast Read Access Times: 200 ns s Low Power CMOS Dissipation: s End of Write Detection: ­Active: 25 mA Max. ­Standby: 100 µA Max. s Simple Write Operation: ­DATA Polling DATA ­RDY/BSY Pin BSY s Hardware Write Protection s CMOS and TTL Compatible I/O s 10,000 Program/Erase Cycles s 10 Year Data Retention s Commercial,Industrial and Automotive ­On-Chip Address and Data Latches ­Self-Timed Write Cycle with Auto-Clear s Fast Write Cycle Time: 10ms Max Temperature Ranges DESCRIPTION The CAT28C17A is a fast, low power, 5V-only CMOS parallel E2PROM organized as 2K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and a RDY/BSY pin signal the start and end of the self-timed write cycle. Additionally, the CAT28C17A features hardware write protection. The CAT28C17A is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 10,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 28-pin DIP and SOIC or 32-pin PLCC packages. BLOCK DIAGRAM A4­A10 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 2,048 x 8 E2PROM ARRAY VCC HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING & RDY/BUSY I/O0­I/O7 A0­A3 ADDR. BUFFER & LATCHES COLUMN DECODER RDY/BUSY 5091 FHD F02 © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 25034-00 2/98 CAT28C17A PIN CONFIGURATION DIP Package (P) RDY/BUSY NC A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 NC OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 SOIC Package (J,K) RDY/BUSY NC A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 NC OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 PLCC Package (N) A7 NC RDY/BUSY 4 3 2 1 32 31 30 29 28 27 26 TOP VIEW 25 24 23 22 A8 A9 NC NC OE A10 CE I/O7 I/O6 9 10 11 12 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 PIN FUNCTIONS Pin Name A0­A10 I/O0­I/O7 RDY/BUSY CE OE WE VCC VSS NC Function Address Inputs Data Inputs/Outputs Ready/BUSY Status Chip Enable Output Enable Write Enable 5V Supply Ground No Connect NC VCC WE NC 5091 FHD F01 MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(1) CIN(1) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V Note: (1) This parameter is tested initi